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ISO-CMOS MT8812 8 x 12 Analog Switch Array
Features
* * * * * * * * * Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 14.5V 14Vpp analog signal capability R ON 65 max. @ V DD=14V, 25C R ON 10 @ V DD=14V, 25C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Low power consumption ISO-CMOS technology
ISSUE 5
November 1988
Ordering Information MT8812AC 40 Pin Ceramic DIP MT8812AE 40 Pin Plastic DIP MT8812AP 44 Pin PLCC 0 to 70C
Description
The Mitel MT8812 is fabricated in MITEL's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input.
Applications
* * * * * PBX systems Mobile radio Test equipment /instrumentation Analog/digital multiplexers Audio/Video switching
STROBE
DATA RESET
VDD
VSS
1 AX0 AX1 AX2 AX3 AY0 AY1 AY2 96
1 ****************
8 x 12 7 to 96 Decoder Latches Switch Array
96
Xi I/O (i=0-11)
*******************
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
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MT8812
ISO-CMOS
40 PIN CERDIP/PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #* 1 2 3 4,5 6,7 8-13 Name Y3 AY2 RESET AX3,AX0 NC X6-X11 Description Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches. Active High. X3 and X0 Address Lines (Inputs). No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 NC No Connection. 15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 NC No Connection. 17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. Ground Reference. 20 VSS 21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs). 24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 NC No Connection. 28 - 33 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. 34 NC No Connection. 35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 NC No Connection. 37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply. 40 VDD
* Plastic DIP and CERDIP only. 3-28
Y7 Y6 STROBE Y5 VSS Y4 AX1 AX2 AY0 AY1 NC 44 PIN PLCC
Y3 AY2 RESET AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 NC Y6 STROBE Y5 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD Y2 DATA Y1 NC Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4
NC NC X6 X7 X8 X9 X10 X11 NC NC NC
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0 NC NC X0 X1 X2 X3 X4 X5 NC NC NC
NC AX0
ISO-CMOS
Functional Description
The MT8812 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input line. Data is asynchro-nously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input line will asynchronously return all memory locations to logical "0" turning off all crosspoint switches.
MT8812
Address Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
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MT8812
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter 1 2 3 4 5 6 Supply Voltage Analog Input Voltage Digital Input Voltage Current on any I/O Pin Storage Temperature Package Power Dissipation PLASTIC DIP CERDIP Symbol VDD VSS VINA VIN I TS PD PD -65 Min -0.3 -0.3 -0.3 VSS-0.3 Max 16.0 VDD+0.3 VDD+0.3 VDD+0.3 15 +150 0.6 1.0 Units V V V V mA C W W
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics 1 2 3 4 Operating Temperature Supply Voltage Analog Input Voltage Digital Input Voltage Sym TO VDD VINA VIN Min 0 4.5 VSS VSS Typ 25 Max 70 14.5 VDD VDD Units C V V V Test Conditions
DC Electrical CharacteristicsCharacteristics 1 Quiescent Supply Current
Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated.
Sym IDD
Min
Typ 1 7
Max 100 15 500 0.8
Units A mA nA V V A
Test Conditions All digital inputs at VIN=VSS or VDD All digital inputs at VIN=2.4V IVXi - VYjI = VDD - VSS See Appendix, Fig. A.1
2 3 4 5
Off-state Leakage Current (See G.9 in Appendix) Input Logic "0" level Input Logic "1" level Input Leakage (digital pins)
IOFF VIL VIH ILEAK 2.4
1
0.1
10
All digital inputs at VIN = VSS or VDD
DC Electrical Characteristics are over recommended temperature range. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym 25C Typ 1 On-state VDD=14V Resistance VDD=12V VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) 2 Difference in on-state resistance between two switches (See G.4 in Appendix) RON 45 60 65 145 Max 65 85 95 220 60C Typ Max 70C Typ Max 75 95 110 260 VSS=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 Units Test Conditions
RON
5
10
10
10
VDD=14V, VSS=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2
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ISO-CMOS
MT8812
AC Electrical Characteristics - Crosspoint Performance-VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics 1 2 3 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel "ON" 20LOG(VOUT/VXi)=-3dB Total Harmonic Distortion (See G.5, G.6 in Appendix) Feedthrough Channel "OFF" Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix).
Sym CS CF F3dB
Min
Typ 20 0.2 45
Max
Units pF pF MHz
Test Conditions f=1 MHz f=1 MHz Switch is "ON"; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 Switch is "ON"; VINA = 2Vpp sinewave f= 1kHz; RL=1k All Switches "OFF"; VINA= 2Vpp sinewave f= 1kHz; RL= 1k. See Appendix, Fig. A.4 VINA=2Vpp sinewave f= 10MHz; RL = 75. VINA=2Vpp sinewave f= 10kHz; RL = 600. VINA=2Vpp sinewave f= 10kHz; RL = 1k. VINA=2Vpp sinewave f= 1kHz; RL = 10k. Refer to Appendix, Fig. A.5 for test circuit. RL=1k; CL=50pF
4 5
THD FDT
0.01 -95
% dB
6
Xtalk
-45 -90 -85 -80
dB dB dB dB
7
Propagation delay through switch
tPS
30
ns
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics - Control and I/O Timings- VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay RESET to Switch Status Delay
Sym CXtalk
Min
Typ 30
Max
Units mVpp
Test Conditions VIN=3V+VDC squarewave; RIN=1k, RL=10k. See Appendix, Fig. A.6 f=1MHz RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF
2 3 4 5 6 7 8 9 10 11 12
CDI FO tDS tDH tAS tAH tSPW tRPW tS tD tR 10 10 10 10 20 40
10 20
pF MHz ns ns ns ns ns ns
40 50 35
100 100 100
ns ns ns
Q Q Q Q Q Q Q Q Q
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Refer to Appendix, Fig. A.7 for test circuit.
Q
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MT8812
ISO-CMOS
tRPW 50% 50%
RESET
tSPW 50% tAS 50% 50%
STROBE
ADDRESS
50%
50% tAH
DATA
50% tDS ON tDH
50%
SWITCH* OFF tD tS tR tR
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AX0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AX1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AX2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AX3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AY0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AY1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
AY2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Connection
X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 No Connection No Connection X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 No Connection No Connection X0-Y1

X11-Y1 X0-Y2 X11-Y2 X0-Y3 X11-Y3 X0-Y4 X11-Y4 X0-Y5 X11-Y5 X0-Y6 X11-Y6 X0-Y7 X11-Y7
Table 1. Address Decode Truth Table
This address has no effect on device status.
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